This invention relates to a clock signal synchronization circuit and method. More particularly, this invention relates to a low-cost clock synchronization circuit that can be implemented using elements in a standard programmable gate-array (PGA).
In digital circuits such as microprocessor circuits, a reference clock signal is distributed throughout the circuits so as to control timing of events within the circuits. In each circuit, the reference clock signal is typically distributed from a single distribution point to various destination points within the circuit. These destination points are at the clock-input pins of integrated circuits (IC""s) that receive the reference clock signal. The destination points may be located at different distances from the distribution point. For reasons which will be discussed later, the signals do not arrive at all these destination points at exactly the same time. The difference in time between the arrivals of the signals is called skew.
Typical paths for a clock signal will include fanout gates, circuit board traces and IC interconnect metal. Each of these provides an opportunity for introducing undesired clock skew. The amount of time it takes a signal to travel along a circuit board trace is called the electrical length of the trace. This electrical length depends upon the physical length and the capacitance of the trace. All else being equal, a signal will take longer to travel a long path than a short one. If the physical lengths of all the clock signal paths are not equal, skew is introduced.
Clock signal paths will often include several levels of fanout gates and buffering. If there are unequal numbers of gates in the signal paths or if there are variations in the time it takes a signal to pass through a gate, skew will occur. How long a signal takes to pass through a gate depends upon several factors, including the propagation delay characteristics of the particular type of gate, the number of loads the gate is driving, and the temperature of the gate. Any variation of these factors between two signal paths will cause skew in the signals. Even if these factors are identical, there may be variations between individual gates of the same type.
There are several reasons for attempting to eliminate as much skew as possible in a circuit. First, skew limits the speed at which a system can operate. Within a microprocessor circuit, tasks are often performed serially, with data being passed from one stage of the circuit to another on subsequent clock cycles. The time period of the clock must be long enough to account for the time it takes a stage to process the data and propagate it to the next stage. In addition, the clock period must also allow for any skew between the clock signals at the various stages. For example, if one stage is clocked late due to clock skew but the next stage is clocked on time, the data from the first stage may not yet be present when the second stage is clocked. The clock period thus must be stretched to accommodate not only the time needed for the first stage to process and propagate the data, but also for the amount of skew between the clock signals present at the two stages.
There are several techniques used in the attempt to reduce clock skew due to one or more of the conditions discussed above. A designer can attempt to equalize the circuit board trace lengths between the clock source and all destinations. This technique is often accomplished by distributing the clock signals radially from a distribution point physically located near the center of the circuit board. The designer can also equalize the number of gates and types of gates in all clock signal paths. Clock skew can also be reduced by equalizing the amount of load that gates and various signal paths must drive. Since these techniques affect the fundamental architecture of the system, they can only be performed during the design of the system. Such techniques cannot account for design changes or component variations. This equalizing technique may not be possible in all circumstances due to other design constraints of the circuit. Additionally, a previously equalized circuit may require the addition of new circuitry not conceived of during the initial design phase. Previously equalized paths may no longer be equalized after the addition of new circuitry.
There are also delay introduction techniques that can be performed during the manufacture or installation of the system. What is important is the difference in delay between the various signal paths, not the actual amount of delay in any given path. Thus, skew between signals can be compensated for by introducing a specific amount of delay in the faster signal paths so as to match the electrical length of the slowest signal path. Delay line tuning involves connecting a clock signal path through a delay line that provides multiple outputs, each output corresponding to a different delay amount. The output corresponding to the needed delay is selected at the time of installation by reference to other clock signal paths. Delay line tuning is adjustable, so it can skew compensate a circuit even after the addition of new circuitry.
These equalizing and delay introduction techniques are useful for large and complex systems that span several system modules. These methods are overkill for small systems wherein skew is introduced mostly due to excessive loading of a reference clock source. In these systems, commercially available phase-locked loop (PLL) circuits can be used to reduce skew. Although these PLLs are accurate and are capable of driving large loads, they are costly and when included in a design, occupies precious printed circuit board space. These PLLs also increases the power consumption of the system.
The prior art therefore creates the need for a low-cost clock synchronization circuit and method for producing an output clock signal that is in synchronization with a reference clock signal.
According to a preferred embodiment of the present invention, a clock synchronization circuit for generating an output clock signal that is substantially in synchronization with a reference clock signal has a programmable delay element and a phase detector. The programmable delay element and the phase detector is preferably implemented using elements in a PGA. The condition of substantial synchronization is reached when the phase difference between the two clock signals is less than a value predetermined during a design stage of the circuit. The programmable delay element is coupled to the reference clock signal for introducing an adjustable delay in the reference clock signal to produce a delay-adjusted delayed output clock signal. By increasing the adjustable delay, the delay-adjusted output clock signal becomes increasingly closer to being in synchronization with the reference clock signal. The phase detector is coupled to the reference clock signal and the delay-adjusted delayed output clock signal for detecting the phase difference between the two clock signals. The adjustable delay is increased until the synchronization condition is reached.
According to another aspect of the invention, a method for generating a delayed output clock signal that is in synchronization with a reference clock signal involves inverting and delaying the reference clock signal by a first delay to produce an intermediate clock signal. This intermediate clock signal cooperates with the reference clock signal to provide a window of width equal to the predetermined delay. The method next introduces an adjustable delay in the intermediate clock signal to produce a delay-adjusted delayed output clock signal. The method also inverts and delays the delay-adjusted delayed output clock signal by a second predetermined delay Y to produce a reference clock signal delayed by the first delay and the second predetermined delay Y. The method increases the adjustable delay to bring a cycle of the delay-adjusted delayed output clock signal to be increasingly in synchronization with a subsequent cycle of the reference clock signal. The adjustable delay is increased until a mark of the reference clock signal delayed by the first delay and the second predetermined delay Y appears in the window. When such a condition is reached, the delay-adjusted delayed output clock signal leads the reference clock signal by a known phase difference X that is equal to the second predetermined delay Y.